Hardware Implementation of GA

Hardware Implementation of GA

Abstract:

A genetic algorithm has been designed with Altera Hardware Description Language (AHDL). The design has also been simulated and implemented with programmable logic devices of Altera's Flex 10K Field Programmable Gate Array (FPGA) family. The genetic algorithm is run on a PC card, which is connected to the central processing unit (CPU) through high-performance Peripheral Component Interconnect (PCI) bus.

Due to the easy reconfigurability of programmable logic devices, experimentation with variable population sizes and various fitness functions is greatly facilitated. This is accomplished by rewriting the AHDL code on the host computer and then reprogramming the chip on the fly through PCI bus.

The main advantage of a hardware-based genetic algorithm is its inherent speed advantage over software-based methods. This speed advantage makes hardware-based genetic algorithm a prime candidate for real time applications, for example optimization of routing in telecommunications networks.

Keywords: programmable hardware , FPGA , hardware GA 

• Introduction
  • Related work
• Hardware implementation
  • Random number generation
  • Mutation
  • Operation of the Pipeline
• Simulations and performance
• Conclusions and future
• Bibliography